Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reductions in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. The timing of operations within a system or circuit is often critical to the proper performance of a device in providing proper results. However, a number of conditions can adversely impact the timing of various operations. For example, fabrication process deviations, voltage drops, and temperature can cause various signal timing variations (e.g., delays) in semiconductor components. Accurate measurement of the timing variations is very important for correct and reliable device performance.
There are a number of different causes of signal timing variations for circuits on different semiconductor chips. For example, changes in device parameters (e.g., transistor parameters) and interconnect metal layer characteristics (e.g., dielectric characteristics) often result in fabrication process discrepancies that produce timing delay variations. The fabrication process discrepancies often produce timing differences or shifts across wafer to wafer, chip to chip, and/or within a chip. Differences in operating temperatures and voltage drops (IR) can also impact timing variations.
Timing variations or differences can have detrimental impacts on the performance of the semiconductor components and uniformity of results. Traditionally, “timing closures” for design are developed to account for and coordinate different timing variations or shifts. For example, designs are often “timing closed” with assumed on chip variation (OCV) numbers and/or with increased timing margin values. Even when timing closure is performed, very little information regarding the actual timing variations and actual timing closure performed on a semiconductor chip typically comes back to the designer for potential use designing future versions or implementations.
It is traditionally very difficult for a designer to determine if problems in a silicon chip performance are related to uneven timing delays. Traditional attempts at measuring timing delays are usually limited and require significant internal and external chip resources. For example, conventional wafer test measurements are often limited to a relatively few places or locations on a wafer (e.g., a process corner). This does not typically provide very good insight to process variations that are encountered in other areas of a chip and from chip to chip. In addition, the actual layout of chip components (e.g., logic units, functional components, gates, etc) can vary (e.g., between chips manufactured at different foundries) making it more difficult to determine impacts on any particular component related to timing variations since the location of a component with respect to a corner measurement can vary.
Traditional attempts at timing variation detection often involve utilizing ring oscillators to obtain an analog indication of a frequency measurement. However, the logistics of traditional attempts at directly measuring and retrieving analog frequency information from ring oscillators makes it very difficult and expensive. Conventional approaches usually involve direct analog measurements of a frequency in which an analog signal is brought off chip and automated test equipment (ATE), oscilloscopes, and/or logic analyzers are used to measure the analog signal. In addition, the analog signals from the ring oscillators traditionally have to be brought off of the chip via dedicated valuable chip input and output (I/O) resources (e.g., bumps, pins). Also, the measurements are typically performed as wafer tests and not performed across wafer lots, making it very difficult for a designer to identify and analyze delay variations for a component across different wafer lots. In addition, information typically available to designers is usually very limited due to the I/O resource consumption requirements of traditional approaches.
Traditional tests are also usually only one time measurements during manufacturing. For example, delay test bumps are not coupled to package pins and so even through a ring oscillator is present in a die, timing variation measurements are not available once the die is packaged. However, timing variations can change over time and adversely impact use of a product in the field after manufacturing.
As the demand for ever more advanced and complicated applications increases, the need for more precise and robust timing variation detection becomes critical. At the same time, decreases in component sizes are making components more sensitive to process, voltage and temperature variations that result in even greater timing delay impacts. For example, in state of the art deep sub micron semiconductor processes the overall process variation is quite large varying in the order of 2 to 2.5 times from best case to worst case operating conditions in the 0.13 um process mode.